Samsung Redesigns Power Delivery for Next-Generation HBM4E Memory
Samsung is making significant advancements in high-bandwidth memory (HBM) technology, specifically targeting the power delivery challenges faced by next-generation AI chips. Following the recent launch of its first commercial HBM4, which consistently achieves speeds of 11.7 Gbps with potential headroom up to 13 Gbps, Samsung is now focusing on the transition to HBM4E memory. This new iteration brings a substantial increase in the number of power bumps—from 13,682 in HBM4 to 14,457 in HBM4E—while maintaining the same physical footprint. The result is denser, thinner wiring, which increases current density and resistance, leading to greater IR drop (voltage loss across the circuit) and additional heat generation. These factors can create a feedback loop that threatens both performance and circuit reliability.
Segmented Power Networks for Enhanced Reliability
To address these engineering challenges, Samsung has reimagined the power delivery network within its HBM4E memory. The traditional large, centralized MET4 power block on the base die—previously organized in expansive honeycomb-like sections near the interposer—has been divided into four smaller, more manageable sections. Additionally, upper metal layers have been further segmented to reduce congestion and shorten routing paths. According to Samsung, these architectural changes have led to a 97% reduction in metal circuit defects compared to HBM4, and a 41% improvement in IR drop. This translates to greater voltage headroom, enabling higher memory speeds and improved reliability for demanding AI workloads.
Exploring Photonic Interconnects for Future HBM-GPU Integration
Looking ahead, Samsung is also investigating innovative approaches to further optimize memory and processor integration. One promising direction involves physically separating HBM memory from the GPU, a move that could alleviate thermal constraints associated with densely packed components. To bridge the increased distance, Samsung is exploring photonic interconnects—optical transmission technologies capable of delivering data at terabit-per-second speeds, vastly outpacing traditional copper connections. With ongoing advancements in substrate wiring, Samsung envisions a future where HBM and GPU could be positioned more than 5 centimeters apart, opening new possibilities for thermal management and system design in high-performance computing.
These developments underscore Samsung’s commitment to pushing the boundaries of memory technology, addressing the complex power and thermal challenges that come with the next generation of AI and high-performance computing hardware.
